1. Field of the Invention
The present invention relates to a solid state imaging device and particularly to a solid state imaging device having reduced residual images, dark current, noise, mixed color, and a high pixel density.
2. Description of the Related Art
Currently, CCD and CMOS solid state imaging devices are extensively used in various video cameras and still cameras. Improvement in performance of solid state imaging devices, such as higher resolutions and higher sensitivity, is always demanded. Technical innovations for higher pixel densities have been made to realize higher resolution solid state imaging devices. Furthermore, technical innovations for lower noise have been made to realize highly sensitive solid state imaging devices.
A prior art solid state imaging device is disclosed in K. Yonemoto, H. Sumi, R. Suzuki, T. Ueno's: “A CMOS Image Sensor with a Simple FPN-Reduction Technology and a Hole Accumulated Diode,” 2000 IEEE International Solid-State Circuits Conference, Digest Papers, MP6. 1 (2000). This prior art CMOS solid state imaging device is shown in FIG. 24A. FIG. 24A is an illustration showing the structure of a pixel of the CMOS solid state imaging device. The CMOS solid state imaging device comprises a PN photodiode PD, a transfer gate TG joined to the PN photodiode PD, a floating diode FD joined to a channel 20 below an electrode of the transfer gate TG, an amplifying MOS transistor 21, a first pixel selection MOS transistor 22 connected to the amplifying MOS transistor 21, a reset MOS transistor 23, and a second pixel selection MOS transistor 24 connected to the transfer gate TG. The PN photodiode PD has a photodiode surface P+ layer 19 on the surface of a photodiode N layer 27. The photodiode surface P+ layer 19 is connected to a channel stopper P+ layer 18. The amplifying MOS transistor 21 has a gate AG connected to the floating diode FD. The reset MOS transistor 23 has a reset gate RG (n) connected to the floating diode FD and a reset drain RD diode. The gates of the first and second pixel selection MOS transistors 22 and 24 are connected to a column scanning circuit joined to a column selection line RL (m). A row selection line CL (n) joined to the source of the second pixel selection MOS transistor 24 and the gate RG (n) of the reset MOS transistor 23 are connected to a row scanning circuit. The reset drain RD of the reset MOS transistor 23 and the drain of the amplifying MOS transistor 21 are connected to a power supply line at voltage Vdd. The source of the first pixel selection. MOS transistor 22 is connected to a signal line 25.
Signal charges (electrons in this case) generated by light irradiation are accumulated in the PN photodiode PD. The accumulated signal charges are transferred to the floating diode FD when an ON voltage is applied to the transfer gate TG. The potential of the floating diode FD changes according to the signal charge packets. At the same time, the gate voltage of the amplifying MOS transistor 21 connected to the floating diode FD changes according to the signal charge packets. When an ON voltage is applied to the gate of the first pixel selection MOS transistor 22, a signal current according to the gate voltage of the amplifying MOS transistor 21 that has changed according to the signal charge packets runs through the signal line 25. The current is read as an output.
FIG. 24B shows the potential profile along a section line A-A in FIG. 24A when an ON voltage is applied to the transfer gate TG and the signal charges accumulated in the photodiode PD are transferred to the floating diode FD. In FIG. 24B, signal charges 26a, 26b, and 26c are shown by hatching for distinction. The signal charges 26a accumulated in the photodiode PD are transferred to the floating diode FD. The signal charges 26b transferred from the floating diode FD modulate the gate voltage of the amplifying MOS transistor 21. Here, among the deepest potential Φmp in the photodiode PD when there is no signal charge, the potential Φtg of the channel 20 when an ON voltage is applied to the transfer gate TG, and the potential Φfg of the floating diode FD when there is no transferred signal charge, Φfg is the deepest, Φtg is the second deepest, and Φmg is the shallowest. The signal charges consist of electrons in the pixel, establishing the relationship Φfg>Φtg>Φmp. The channel stopper P+ layer 18 has a potential of 0 V. The potential profile relationship allows most signal charges in the photodiode PD to be transferred to the floating diode FD. Consequently, trailing residual images can be prevented when images of moving objects are captured. Furthermore, the above structure can prevent kTC noise, which otherwise causes deteriorated sensitivity. The signal charges 26b in the floating diode FD are removed through the reset drain RD when a voltage is applied to the reset gate RG (n). In such a case, a certain level of charges 26c remains in the floating diode FD.
The signal charges can completely be transferred from the photodiode PD to the floating diode FD when the P+ layer 19 on the surface of the N layer 27 of the photodiode PD (“the photodiode surface P+ layer” hereafter) is connected to the channel stopper P+ layer 18 to which 0 V is applied so that the photodiode surface P+ layer 19 is fixed (pinned) to 0 V. FIG. 24C shows the potential profile through the SiO2 film, photodiode surface P+ layer 19, photodiode N layer 27, and photodiode P layer 28 along a section line B-B in FIG. 24A. FIG. 24C shows signal charges 26d by hatching for distinction. The deepest potential Φmp in the photodiode PD when there is no signal charge is within the photodiode N layer 27. Therefore, the signal charges 26d are present in the inner photodiode N layer 27 and photodiode P layer 28 rather than in the photodiode surface P+ layer 19 of which the potential is pinned. Holes 29 are accumulated in the photodiode surface P+ layer 19. The holes 29 are recombined to electrons thermally excited due to the SiO2-Si interface states and prevent the electrons infusing into the signal charges 26d, and no dark current occurs.
If the CMOS solid state imaging device shown in FIG. 24A does not have the photodiode PD surface P+ layer 19 joined to the channel stopper P+ layer 18 having a fixed potential of 0V, the photodiode PD can directly be connected to the gate AG of the amplifying MOS transistor 21. In this way, the voltage of the gate AG of the amplifying MOS transistor 21 can directly be changed according to the signal charges accumulated in the photodiode PD for imaging operation. However, such a structure may cause residual images and increase kTC noise and dark current as mentioned above. On the other hand, the photodiode PD surface P+ layer 19 does not allow a contact hole to be formed on the photodiode PD so as to connect the photodiode PD to the gate AG of the amplifying MOS transistor 21 via metal wiring through the contact hole. Therefore, the transfer gate TG and floating diode FD have to newly be added. Such newly added regions hamper increase in the pixel density.
Other problems of prior art CMOS solid state imaging devices include deteriorated resolution and mixed color in color imaging.